Method of manufacturing flat panel display device

ABSTRACT

A flat panel display device with improved electrical characteristics and a simplified manufacturing process is disclosed. The device includes a semiconductor layer formed on an insulating substrate; source and drain electrodes directly contacting both end portions of the semiconductor layer, respectively; a pixel electrode having an opening portion formed thereon; a first insulating layer formed over the remaining portion of the insulating substrate except for the opening portion; a gate electrode formed on a portion of the first insulating layer over the semiconductor layer; and source and drain regions formed in both end portions of the semiconductor layer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a flat panel display device anda method of a manufacturing the same, and, more particularly, to a flatpanel display device with improved electrical characteristics andreduced current leakage.

[0003] 2. Description of Related Art

[0004]FIG. 1 is a cross-sectional view illustrating a conventionalorganic EL display device. A method of manufacturing the conventionalorganic EL display device is described below with reference to FIG. 1.

[0005] A buffer layer 12 is formed on a transparent substrate 11. Thetransparent substrate 11 is made of a glass or a synthetic resin. A polysilicon layer is deposited on the buffer layer 12 and patterned into asemiconductor layer 20 using a first mask. A first insulating layer 25is formed over the entire surface of the transparent substrate 11.

[0006] Then, a first metal layer is deposited on the first insulatinglayer 25 and patterned into a gate electrode 35 using a second mask.Using the gate electrode 35 as a mask, an n-type impurity or a p-typeimpurity is ion-implanted into the semiconductor layer 20 to form sourceand drain regions 26 and 27.

[0007] Thereafter, a second insulating layer 30 is formed over theentire surface of the transparent substrate 11. The second insulatinglayer 30 serves as an interlayer insulating layer. Using a third mask,contact holes 31 and 32 are formed in the interlayer insulating layer30. The contact holes 31 and 32 expose portions of the source and drainregions 26 and 27, respectively.

[0008] A second metal layer is deposited on the second insulating layer30, filling into the contact holes 31 and 32. The second metal layer ispatterned using a fourth mask to form source and drain electrodes 50 and55. The source and drain electrodes 50 and 55 are electrically connectedto the source and drain regions 26 and 27 through the contact holes 31and 32, respectively.

[0009] Subsequently, a third insulating layer 40 is formed over theentire surface of the transparent substrate 11. Using a fifth mask, thethird insulating layer 40 is etched to form a via hole 41 at a locationcorresponding to either of the source and drain electrodes 50 and 55. InFIG. 1, the via hole 41 is formed at a location corresponding to aportion of the drain electrode 55.

[0010] A transparent conductive material layer is deposited on the thirdinsulating layer 40 and patterned using a sixth mask to form a pixelelectrode 60. The pixel electrode 60 serves as an anode electrode. Thepixel electrode 60 is electrically connected to either of the source anddrain electrodes 50 and 55 through the via hole 41. In FIG. 1, the pixelelectrode 40 is electrically connected to the drain electrode 55 throughthe via hole 41.

[0011] A fourth insulating layer 70 is formed over the entire surface ofthe transparent substrate 11. The fourth insulating layer 70 serves as aplanarization layer. The fourth insulating layer 70 is etched using aseventh mask to form an opening portion 71. The opening portion 71exposes a portion of the pixel electrode 60. An organic EL layer 80 isformed on the exposed portion of the pixel electrode 60 to cover theopening portion 71. Then, a cathode electrode 90 is formed to cover theorganic EL layer 80. Therefore, the conventional organic EL displaydevice is completed.

[0012] As described above, the method of manufacturing the conventionalorganic EL display device requires a seven-mask process. Therefore, thispresents the difficulty that the manufacturing process is complicatedand the production cost is increased.

[0013] Also, since the gate electrode 35 is used as a mask during anion-implanting process to form the source and drain regions 26 and 27,the gate electrode 35 may become damaged during manufacturing, therebydeteriorating electrical characteristics of the flat panel displaydevice.

[0014] In addition, when a lightly doped drain (LDD) structure or anoffset structure is employed in order to improve an on/off currentratio, an additional mask process is required. In that case, a processto anodize the gate electrode can be employed so that an additional maskprocess is not required. However, this requires additional equipment forthe anodizing process, thereby increasing the production cost.

SUMMARY OF THE INVENTION

[0015] To overcome the difficulties described above, preferredembodiments of the present invention provide a flat panel display devicehaving a simplified manufacturing process.

[0016] It is another object of the present invention to provide a flatpanel display device having excellent electrical characteristics.

[0017] It is a still object of the present invention to provide a flatpanel display device which can reduce a leakage current.

[0018] In order to achieve the above objects, the preferred embodimentsof the present invention provide a flat panel display device,comprising: a semiconductor layer formed on an insulating substrate;source and drain electrodes directly contacting both end portions of thesemiconductor layer, respectively; a pixel electrode having an openingportion formed thereon; a first insulating layer formed over theremaining portion of the insulating substrate except for the openingportion; a gate electrode formed on a portion of the first insulatinglayer over the semiconductor layer; and source and drain regions formedin both end portions of the semiconductor layer.

[0019] The source and drain electrodes include a pixel electrodematerial layer, a metal material layer and a capping insulating materiallayer stacked sequentially. The pixel electrode extends from either ofthe source and drain electrodes. The organic EL display device furtherincludes a storage capacitor including first and second capacitorelectrodes with a dielectric layer interposed therebetween. The firstcapacitor electrode includes the pixel electrode material layer and themetal material layer stacked sequentially. The second capacitorelectrode includes a gate electrode material layer. The dielectric layerincludes the capping insulating layer and the first insulating layerstacked sequentially.

[0020] The source and drain regions include an offset region formed in aportion of the semiconductor layer between the source and drainelectrodes and the gate electrode. The source and drain regions includelow-density source and drain regions formed in a portion of thesemiconductor layer between the source and drain electrodes and the gateelectrode, thereby forming a lightly doped drain (LDD) structure.

[0021] The organic EL display device further includes first and secondspacers. The first spacer is formed on side wall portions of the sourceand drain regions. The second spacer is formed on side wall portions ofthe gate electrode and the opening portion. The organic EL displaydevice further includes a second insulating layer for planarization onthe remaining portion of the first insulating layer except for theopening portion. The gate electrode includes a metal material layer anda capping insulating layer stacked sequentially.

[0022] The present invention further provides a method of manufacturinga flat panel display device, comprising: forming a semiconductor layeron an insulating layer; ion-implanting an impurity having a firstconductivity into the semiconductor layer; forming source and drainelectrodes, the source and drain electrodes directly contacting both endportions of the semiconductor layer; ion-implanting an impurity having asecond conductivity into the semiconductor layer to form high-densitysource and drain regions and a channel area, the high-density source anddrain regions directly contacting the source and drain electrodes;forming a first insulating layer over the entire surface of theinsulating substrate; forming a pixel electrode having an openingportion formed thereon; and forming a gate electrode on a portion of thefirst insulating layer over the semiconductor layer.

[0023] The method further includes forming a contact holecontemporaneously with forming the pixel electrode having the openingportion, the contact hole contacting the first capacitor electrode andthe gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] For a more complete understanding of the present invention andthe advantages thereof, reference is now made to the followingdescriptions taken in conjunction with the accompanying drawings, inwhich like reference numerals denote like parts, and in which:

[0025]FIG. 1 is a cross-sectional view illustrating a conventionalorganic EL display device;

[0026]FIG. 2 is a plan view illustrating an embodiment of an organic ELdisplay device according to the present invention;

[0027]FIGS. 3A to 3H are cross-sectional views taken along line III-IIIof FIG. 2;

[0028]FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 2;and

[0029]FIG. 5 is a cross-sectional view illustrating another embodimentof the organic EL display device according to the present invention.

DETAILED DESCRIPTION OF PREFFERED EMBODIMENTS

[0030] Reference will now be made in detail to preferred embodiments ofthe present invention, examples of which are illustrated in theaccompanying drawings.

[0031]FIG. 2 is a plan view illustrating an embodiment of an organic ELdisplay device according to the present invention.

[0032] The organic EL display device 100 includes a plurality of pixels.Of the plurality of the pixels, FIG. 2 shows only one pixel. The pixelis formed at a pixel region 140 defined by a gate line 120, a data line130, and a power supply line 135.

[0033] The gate line 120 is arranged in a transverse direction andapplies an on/off signal of a thin film transistor (TFT). The data line130 is arranged in a direction perpendicular to the gate line 120 andapplies a data voltage. The power supply line 135 is spaced apart fromthe data line and is also arranged in a perpendicular to the gate line120. Electrical power is applied to the power supply line 135 while theorganic EL display device 100 is driven.

[0034] The pixel includes a first TFT 150, a storage capacitor 190, asecond TFT 200, and an organic EL element 300.

[0035] The first TFT 150 includes a semiconductor layer 160, source anddrain electrodes 170 and 175, respectively, and a gate electrode 180.The source and drain electrodes 170 and 175 contact both end portions ofthe semiconductor layer 160, respectively. The source electrode 170extends from the data line 130, and the gate electrode 180 extends fromthe gate line 120.

[0036] The storage capacitor 190 includes first and second capacitorelectrodes 193 and 197, respectively. The first capacitor electrode 193is electrically connected to the drain electrode 175 of the first TFT150. The second capacitor electrode 197 is electrically connected to thepower supply line 135 through a contact hole 262.

[0037] The second TFT 200 includes a semiconductor layer 210, source anddrain electrodes 235 and 236, respectively, and a gate electrode 270.The source and drain electrodes 235 and 236 contact both end portions ofthe semiconductor layer 210, respectively. The source electrode 235extends from the power supply line 135, and the gate electrode 270 iselectrically connected to the first capacitor electrode 193 through acontact hole 261.

[0038] The organic EL element 300 includes a pixel electrode 310 and anorganic EL light-emitting layer 320. The pixel electrode 310 extendsfrom either of the source and drain electrodes 235 and 236 of the secondTFT 200. In FIG. 2, the pixel electrode 310 extends from the drainelectrode 236 of the second TFT 200.

[0039] A method of manufacturing the organic EL display device accordingto the present invention is described below with reference to FIGS. 3Ato 3H and to FIG. 4.

[0040] Referring now to FIGS. 3A and 4, a buffer layer 205 is formed ona transparent substrate 110. Preferably, the buffer layer 205 is made ofSiO2. An amorphous silicon layer is deposited on the buffer layer 205.The amorphous silicon layer is crystallized by, for example, a laserannealing process to form a poly silicon layer. The poly silicon layeris patterned using a first mask (not shown) to form the semiconductorlayer 160 of the first TFT 150 and the semiconductor layer 210 of thesecond TFT 200. The buffer layer 205 serves to shield the impuritiessuch as an Na-ion from being diffused into the semiconductor layers 160and 210. Thereafter, a first ion-implanting process is performed: ahigh-density impurity having a predetermined conductivity, e.g., ap+-type impurity, is ion-implanted into the entire surface of thesemiconductor layers 160 and 210.

[0041] Referring now to FIGS. 3B and 4, a transparent conductivematerial layer 310 a, a first metal layer 230 a and a first insulatinglayer 240 a are sequentially deposited over the entire surface of thetransparent substrate 110.

[0042] Referring now to FIGS. 3C and 4, the transparent conductivematerial layer 310 a, the first metal layer 230 a and the firstinsulating layer 240 a are simultaneously patterned using a second mask(not shown) to expose respective central portions of the semiconductorlayers 160 and 210, thereby forming the source and drain electrodes 170and 175 of the first TFT 150, the source and drain electrodes 235 and236 of the second TFT 200 and the first capacitor electrode 193.

[0043] The source and drain electrodes 170 and 175 of the first TFT 150directly contact both end portions of the semiconductor layer 160,respectively, and have a multi-layered structure (i.e., three-layeredstructure).

[0044] The source and drain electrodes 235 and 236 of the second TFT 200directly contact both end portions of the semiconductor layer 210,respectively, and have a multi-layered structure (i.e., three-layeredstructure).

[0045] The first capacitor electrode 193 has a dual-layered structureincluding the transparent conductive material layer 310 a and the firstmetal layer 230 a.

[0046] At the same time, the data line 130 and the power supply line 135are formed and also have a dual-layered structure including thetransparent conductive material layer 310 a and the first metal layer230 a.

[0047] Preferably, the transparent conductive material layer 310 aincludes one of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0048] Subsequently, referring now to FIGS. 3D and 4, a secondinsulating layer is deposited over the entire surface of the transparentsubstrate 110 and is anisotropically etched to form a first spacer 250on side wall portions of the source and drain electrodes 170 and 175 andon the side wall portion of the source and drain electrodes 235 and 236,respectively. Thereafter, a second ion-implanting process is performed:a high-density impurity having an opposite conductivity to that of thefirst ion-implanting process (i.e., n+-type impurity) is ion-implantedinto the exposed portions of the semiconductor layers 160 and 210. As aresult, the central portions of the semiconductor layers 160 and 210enter a non-ion doped state and thus serve as a channel area. Also, bothend portions of the semiconductor layers 160 and 210, under the sourceand drain electrodes 170, 175, 235, and 236 and the first spacer 250,serve as high-density source and drain regions 161, 162, 211, and 212.

[0049] The first spacer 250 is used to control an area size of thesource and drain regions formed by the second ion-implanting process.Thus, the second ion-implanting process can be performed without aprocess of forming the spacer 250. This simplifies the manufacturingprocess.

[0050] During the second ion-implanting process, the first insulatinglayer 240 a on the source and drain electrodes 170, 175, 235, and 236serves as an ion-implanting barrier to prevent the source and drainelectrodes 170, 175, 235, and 236 from being damaged by the impurity,thereby preventing defects of the source and drain electrodes 170, 175,235, and 236 such as a hillock and a crack.

[0051] Next, referring now to FIGS. 3E and 4, a third insulating layer260 is formed over the entire surface of the transparent substrate 110.A portion of the first insulating layer 240 a and a portion of the thirdinsulating layer 260 over the first capacitor electrode 193 serve as adielectric layer 195. Thereafter, using a third mask (not shown), thefirst metal layer 230 a, the first insulating layer 240 a and the thirdinsulating layer 260 are simultaneously etched to form an openingportion 265, thereby exposing a portion of the pixel electrode 310extending from the drain electrode 236. At the same time, the first andsecond contact holes 261 and 262 are formed.

[0052] Referring now to FIGS. 3F and 4, a second metal layer and afourth insulating layer are sequentially deposited on the thirdinsulating layer 260 and patterned using a fourth mask to form the gateelectrode 180 of the first TFT 150 and the gate electrode 270 of thesecond TFT 200. The gate electrodes 180 and 270 include a capping layer280 formed thereon. At the same time, the second capacitor electrode 197is formed. The second capacitor electrode 197 includes a metal layer 180a and the capping layer 280. The gate electrode 270 of the second TFT200 is electrically connected to the first capacitor electrode 193through the first contact hole 261, and the power supply line 135 iselectrically connected to the second capacitor electrode 197 through thesecond contact hole 262.

[0053] Referring now to FIGS. 3G and 4, a fifth insulating layer isdeposited over the entire surface of the transparent substrate 110 andis anisotropically etched to from a second spacer 290 on both side wallportions of the gate electrodes 180 and 270. Thereafter, a thirdion-implanting process is performed: a low-density impurity, i.e., ap-type low-density impurity, is ion-implanted into the semiconductorlayers 160 and 210 to form low-density source and drain regions 164,165, 213, and 214, whereby a lightly doped drain (LDD) structure isformed.

[0054] At this time, when the third ion-implanting process is notperformed, the regions 164, 165, 213, and 214 serve as an offset region,and thus an offset structure is formed.

[0055] The capping layer 280 serves as an ion-implanting barrier toprevent the gate electrodes 180 and 270 from being damaged by theimpurity.

[0056] Referring now to FIGS. 3H and 4, the organic EL light-emittinglayer 320 is formed on the exposed portion of the pixel electrode 310 tocover the opening portion 265. Then, a cathode electrode 330 is formedto cover the organic EL light-emitting layer 320. The cathode electrode330 is made of a material having a work function lower than does theanode electrode 310.

[0057] As described above, the organic EL display device according tothe present invention is seen to be manufactured through a process thatrequires only four masks.

[0058]FIG. 5 is a cross-sectional view illustrating another embodimentof the organic EL display device according to the present invention. Theorganic EL display device of FIG. 5 includes a planarization layer 340that is formed after the second spacer 290 is formed during the processdepicted in FIG. 3G. At this juncture, a process of forming the secondspacer 290 can be omitted. Therefore, to manufacture the organic ELdisplay device of FIG. 5 requires a five-mask process.

[0059] As described previously, conventional techniques require aseven-mask process. Therefore, since only a four-mask process or afive-mask process is used to manufacture the organic EL display deviceaccording to the present invention, the manufacturing process issimplified, thereby improving the manufacturing yield. Also, since thecapping layers are formed on the source and drain electrodes and thegate electrodes in the present invention, it is possible to prevent thesource and drain electrodes and the gate electrodes from being damagedby the impurity during the ion-implanting process. This providesimproved electrical characteristics. In addition, since the organic ELdisplay device can have an LDD structure or an offset structure, theleakage current can be reduced without an additional process.

[0060] The present invention is described focusing on the organic ELdisplay device, but those skilled in the art will readily recognize thatit can be applied to other flat panel display devices.

[0061] While the invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

What is claimed is:
 1. A flat panel display device, comprising: asemiconductor layer formed on an insulating substrate; source and drainelectrodes directly contacting a first end portion and a second endportion of the semiconductor layer, respectively; a pixel electrodehaving an opening portion formed thereon; a first insulating layerformed over the remaining portion of the insulating substrate except forthe opening portion; a gate electrode formed on a portion of the firstinsulating layer formed over the semiconductor layer; and source anddrain regions formed in the first end portion and the second end portionof the semiconductor layer.
 2. The device of claim 1, wherein the sourceand drain electrodes include a pixel electrode material layer, a metalmaterial layer, and a capping insulating material layer, each stackedsequentially.
 3. The device of claim 2, wherein the pixel electrodeextends from either of the source and drain electrodes.
 4. The device ofclaim 2, further comprising, a storage capacitor including first andsecond capacitor electrodes with a dielectric layer interposedtherebetween, the first capacitor electrode including the pixelelectrode material layer and the metal material layer, each stackedsequentially, the second capacitor electrode including a gate electrodematerial layer, the dielectric layer including the capping insulatingmaterial layer and the first insulating layer, each stackedsequentially.
 5. The device of claim 1, wherein the source and drainregions include an offset region formed in a portion of thesemiconductor layer between the source and drain electrodes and the gateelectrode.
 6. The device of claim 1, wherein the source and drainregions include low-density source and drain regions formed in a portionof the semiconductor layer between the source and drain electrodes andthe gate electrode, thereby forming a lightly doped drain structure. 7.The device of claim 1, further comprising, first and second spacers, thefirst spacer formed on side wall portions of the source and drainregions, the second spacer formed on side wall portions of the gateelectrode and the opening portion.
 8. The device of claim 1, furthercomprising, a second insulating layer for planarization on the remainingportion of the first insulating layer except for the opening portion. 9.The device of claim 1, wherein the gate electrode includes a metalmaterial layer and a capping insulating layer, each stackedsequentially.
 10. A method of manufacturing a flat panel display device,comprising: forming a semiconductor layer on an insulating layer;ion-implanting an impurity having a first conductivity into thesemiconductor layer; forming source and drain electrodes, the source anddrain electrodes directly contacting a first end portion and a secondend portion of the semiconductor layer; ion-implanting an impurityhaving a second conductivity into the semiconductor layer to formhigh-density source and drain regions and a channel area, thehigh-density source and drain regions directly contacting the source anddrain electrodes; forming a first insulating layer over an entiresurface of the insulating substrate; forming a pixel electrode having anopening portion formed thereon; and forming a gate electrode on aportion of the first insulating layer formed over the semiconductorlayer.
 11. The method of claim 10, wherein the source and drainelectrodes include a pixel electrode material layer, a metal materiallayer and a capping insulating material layer, each stackedsequentially.
 12. The method of claim 10, wherein the pixel electrodeexposed through the opening portion is formed by sequentially etchingthe first insulating layer, a capping insulating layer and a metalmaterial layer, each stacked sequentially.
 13. The method of claim 12,further comprising, a storage capacitor including first and secondcapacitor electrodes with a dielectric layer interposed therebetween,the first capacitor electrode extending from either of the source anddrain electrodes and including the pixel electrode material layer andthe metal material layer, each stacked sequentially, the secondcapacitor including a gate electrode material layer, the dielectriclayer electrode formed on the first capacitor electrode and includingthe capping insulating layer and the first insulating layer, eachstacked sequentially.
 14. The method of claim 13, further comprising,forming a contact hole contemporaneously with forming the pixelelectrode having the opening portion, the contact hole contacting thefirst capacitor electrode and the gate electrode.